AT90PWM3B-16MU Atmel, AT90PWM3B-16MU Datasheet - Page 219
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AT90PWM3B-16MU
Manufacturer Part Number
AT90PWM3B-16MU
Description
IC MCU AVR RISC 8K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Package
32QFN EP
Device Core
AVR
Family Name
90P
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
27
Interface Type
SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
2
Processor Series
AT90PWMx
Core
AVR8
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Dac
10 bit, 1 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM3B-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT90PWM3B-16MUR
Manufacturer:
TI
Quantity:
1 829
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19.5.3
19.5.4
19.5.5
4317J–AVR–08/10
Receiving 17 Data Bit Frames
Receive Complete Flag and Interrupt
Receiver Error Flags
The following code example shows a simple EUSART receive function.
Note:
In this configuration the seventeenth bit shoud be read from the RXB8 bit register, the rest of the
most significant bits (9, 10, 11, 12, 13, 14, 15 and 16) should be read from the EUDR register,
before the low byte of the character is read from UDR.
The EUSART Receiver has the same USART flag that indicates the Receiver state.
See “Receive Complete Flag and Interrupt” in USART section.
When the EUSART is not configured in Manchester mode, the EUSART has the three same
errors flags as standard mode: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE).
All can be accessed by reading UCSRA. (See “Receiver Error Flags” in USART section).
When the EUSART is configured in Machester mode, the EUSART has two errors flags: Data
OverRun (DOR), and Manchester framing error (FEM bit of EUCSRC).
Assembly Code Example
C Code Example
TABLE 3.
EUSART_Receive:
unsigned int EUSART_Receive( void )
{
}
; Wait for data to be received
sbis UCSRA, RXC
rjmp EUSART_Receive
; Get MSB (r15), LSB (r16)
lds
lds
ret
unsigneg int rx_data
/* Wait for data to be received */
while ( !(UCSRA & (1<<RXC)) )
/* Get and return received data from buffer */
rx_data=EUDR;
rx_data=rx_data<<8+UDR;
return rx_data;
The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS”
and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
r15, EUDR
r16, UDR
;
(1)
(1)
AT90PWM2/3/2B/3B
219
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