ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 10
![MCU AVR 8K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY84-15MZ
Manufacturer Part Number
ATTINY84-15MZ
Description
MCU AVR 8K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY84-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
512 x 8
Program Memory Size
8KB (8K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY84-15MZ
Manufacturer:
ATMEL
Quantity:
480
Part Number:
ATTINY84-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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5.5
5.5.1
10
General Purpose Register File
Atmel ATtiny24/44/84 [Preliminary]
The X-register, Y-register, and Z-register
The register file is optimized for the Atmel
achieve the required performance and flexibility, the following input/output schemes are sup-
ported by the register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 5-2 on page 10
CPU.
Figure 5-2.
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in
directly into the first 32 locations of the user data space. Although not physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the regis-
ters, as the X-, Y- and Z-registers can be set to index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage. These
registers are 16-bit address pointers for indirect addressing of the data space. The three indi-
rect address registers X, Y, and Z are defined as described in
Registers
Purpose
Working
General
Figure
AVR CPU General Purpose Working Registers
5-2, each register is also assigned a data memory address, mapping them
shows the structure of the 32 general purpose working registers in the
7
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
…
…
®
AVR
0
®
Enhanced RISC instruction set. In order to
Addr.
0x0D
0x0E
0x1A
0x1B
0x1C
0x1D
0x1E
0x00
0x01
0x02
0x0F
0x10
0x11
0x1F
Figure 5-3 on page
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
7701D–AVR–09/10
11.
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