ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 135

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.3
7701D–AVR–09/10
DIDR0 – Digital Input Disable Register 0
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logical one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logical one and the I-bit in the status register is set, the analog
comparator interrupt is activated. When written logical zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logical one, this bit enables the input capture function in timer/counter 1 to be
triggered by the analog comparator. The comparator output is in this case directly connected
to the input capture front-end logic, making the comparator utilize the noise canceller and
edge select features of the timer/counter 1 input capture interrupt. When written logical zero,
no connection between the analog comparator and the input capture function exists. To make
the comparator trigger the timer/counter 1 input capture interrupt, the ICIE1 bit in the timer
interrupt mask register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events trigger the analog comparator interrupt. The
different settings are shown in
Table 17-2.
When changing the ACIS1/ACIS0 bits, the analog comparator interrupt must be disabled by
clearing its interrupt enable bit in the ACSR. Otherwise, an interrupt can occur when the bits
are changed.
• Bits 1, 0 – ADC0D,ADC1D: ADC 1/0 Digital input buffer disable
When this bit is written logical one, the digital input buffer on the AIN1/0 pin is disabled. The
corresponding PIN register bit will always read as zero when this bit is set. When an analog
signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit
should be written logical one to reduce power consumption in the digital input buffer.
Bit
0x01 (0x21)
Read/Write
Initial Value
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ADC7D
R/W
7
0
ACIS0
0
1
0
1
ADC6D
R/W
6
0
Atmel ATtiny24/44/84 [Preliminary]
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
ADC5D
R/W
5
0
17-2.
ADC4D
R/W
4
0
ADC3D
R/W
3
0
ADC2D
R/W
2
0
ADC1D
R/W
1
0
ADC0D
R/W
0
0
DIDR0
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