ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 8

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
5.4
8
ALU – Arithmetic Logic Unit
Status Register
Atmel ATtiny24/44/84 [Preliminary]
The fast-access register file contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the register file, the operation is executed,
and the result is stored back in the register file, all in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data
space addressing, enabling efficient address calculations. One of the address pointers can
also be used as an address pointer for look up tables in flash program memory. These added
function registers are the 16-bit X-, Y-, and Z-registers, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant
and a register. Single-register operations can also be executed in the ALU. After an arithmetic
operation, the status register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions able to
directly address the whole address space. Most AVR
format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on
the stack. The stack is effectively allocated in the general data SRAM, and consequently the
stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the stack pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The SP is read/write accessible in the I/O space. The data SRAM
can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the Atmel
A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the
interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions such as control
registers, SPI, and other I/O functions. The I/O memory can be accessed directly or as the
data space locations following those of the register file, 0x20 - 0x5F.
The high-performance Atmel
pose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories - arithmetic, logical, and bit functions. Some implemen-
tations of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. See the "Instruction Set" section for a detailed description.
The status register contains information about the result of the most recently executed arith-
metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the status register is updated after all ALU operations, as
specified in the instruction set summary. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
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AVR
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AVR
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ALU operates in direct connection with all 32 general pur-
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architecture are all linear and regular memory maps.
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instructions have a single 16-bit word
7701D–AVR–09/10
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