AT90CAN32-16AUR Atmel, AT90CAN32-16AUR Datasheet - Page 304

• Manufacturer Part Number: AT90CAN32-16AUR
• Description: MCU AVR 32K FLASH 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN32-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.5
23.5.1
23.5.2
23.6
23.6.1
304
Boundary-scan Related Register in I/O Memory
Boundary-scan Chain
AT90CAN32/64/128
MCU Control Register – MCUCR
MCU Status Register – MCUSR
Scanning the Digital Port Pins
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
Figure 23-3
cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a
bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –
ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are
not used in the following description
The Boundary-scan logic is not included in the figures in the datasheet.
simple digital port pin as described in the section
details from
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The
Figure 23-3
JTD
R/W
R
7
0
7
–
0
R
R
replaces the dashed box in
6
–
0
6
–
0
R
5
–
0
5
–
R
0
JTRF
PUD
R/W
R/W
4
0
4
WDRF
R/W
R
3
–
0
3
“I/O-Ports” on page
See Bit Description
Figure
BORF
R/W
R
2
–
0
2
23-4.
EXTRF
IVSEL
R/W
R/W
1
0
1
66. The Boundary-scan
PORF
IVCE
R/W
R/W
Figure 23-4
0
0
0
MCUCR
MCUSR
7679H–CAN–08/08
shows a