AT90CAN32-16AUR Atmel, AT90CAN32-16AUR Datasheet - Page 58

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AT90CAN32-16AUR

Manufacturer Part Number
AT90CAN32-16AUR
Description
MCU AVR 32K FLASH 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheets

Specifications of AT90CAN32-16AUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Mounting Style
SMD/SMT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90CAN32-16AUR
Manufacturer:
Atmel
Quantity:
10 000
7.3.1
58
AT90CAN32/64/128
Watchdog Timer Control Register – WDTCR
• Bits 7..5 – Reserved Bits
These bits are reserved bits for future use.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits.
Watchdog Timer” on page 59.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 59.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 7-6.
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
WDP2
Initial Value
Read/Write
0
0
0
0
1
1
1
1
Bit
ten to WDE even though it is set to one before the disable operation starts.
WDP1
Table
0
0
1
1
0
0
1
1
Watchdog Timer Prescale Select
R
7
0
See “Timed Sequences for Changing the Configuration of the Watchdog
7-6.
WDP0
0
1
0
1
0
1
0
1
R
6
0
See “Timed Sequences for Changing the Configuration of the
Oscillator Cycles
R
5
0
Number of WDT
32/64K cycles
1,024K cycles
2,048K cycles
256K cycles
512K cycles
16K cycles
32K cycles
64K cycles
WDCE
R/W
0
4
WDE
R/W
3
0
Typical Time-out at
WDP2
R/W
2
0
V
CC
17.1 ms
34.3 ms
68.5 ms
0.14 s
0.27 s
0.55 s
1.1 s
2.2 s
= 3.0V
WDP1
R/W
1
0
WDP0
R/W
0
0
Typical Time-out at
WDTCR
V
CC
16.3 ms
32.5 ms
7679H–CAN–08/08
65 ms
0.13 s
0.26 s
0.52 s
1.0 s
2.1 s
= 5.0V

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