DSPIC30F2011-30I/ML Microchip Technology, DSPIC30F2011-30I/ML Datasheet - Page 21

• Manufacturer Part Number: DSPIC30F2011-30I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2011-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DAF30-4 - DEVICE ATP FOR ICE4000
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201130IML

6.6
To allow portability of code, the programmer must read
the
hexadecimal file. If configuration information is not
present in the hexadecimal file, a simple warning
message should be issued by the programmer.
Similarly, while saving a hexadecimal file, all
configuration information must be included. An option
to not include the configuration information can be
provided.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.
6.7
The dsPIC30F devices contain 32 instructions of Unit
ID. These are located at addresses 0x8005C0 through
0x8005FF. The Unit ID can be used for storing product
information
manufacturing dates, manufacturing lot numbers and
other such application-specific information.
A Bulk Erase does not erase the Unit ID locations.
Instead, erase all executive memory using steps 1-4 as
shown in
with the programming executive. Alternately, use a
Row Erase to erase the row containing the Unit ID
locations.
6.8
Checksums for the dsPIC30F are 16 bits in size. The
checksum is to total sum of the following:
• Contents of code memory locations
• Contents of Configuration registers
Table A-1
each device. All memory locations are summed one
byte at a time, using only their native data size. More
specifically, Configuration and device ID registers are
summed by adding the lower two bytes of these
locations (the upper byte is ignored), while code
memory is summed by adding all three bytes of code
memory.
© 2010 Microchip Technology Inc.
Note:
Configuration
Configuration Information in the
Hexadecimal File
Unit ID
Checksum Computation
describes how to calculate the checksum for
Table
The
depending on the code-protect setting.
Table A-1
checksum for an unprotected device and
a read-protected device. Regardless of
the code-protect setting, the Configuration
registers can always be read.
such
12-1, and program the Unit ID along
checksum
as
register
describes how to compute the
serial
locations
calculation
numbers,
from
system
differs
the
7.0
7.1
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
is described in
Commands”. The response set is described in
Section 9.0 “Programming Executive
7.2
The Enhanced ICSP interface is a 2-wire SPI interface
implemented using the PGC and PGD pins. The PGC
pin is used as a clock input pin, and the clock source
must be provided by the programmer. The PGD pin is
used for sending command data to, and receiving
response data from, the programming executive. All
serial data is transmitted on the falling edge of PGC
and latched on the rising edge of PGC. All data
transmissions are sent Most Significant bit (MSb) first,
using 16-bit mode (see
FIGURE 7-1:
Since a 2-wire SPI interface is used, and data transmis-
sions are bidirectional, a simple protocol is used to
control the direction of PGD. When the programmer
completes a command transmission, it releases the
PGD line and allows the programming executive to
drive this line high. The programming executive keeps
the PGD line high to indicate that it is processing the
command.
After the programming executive has processed the
command, it brings PGD low for 15 μsec to indicate to
the programmer that the response is available to be
PGC
PGD
1
P1a
MSb
P1b
2
PROGRAMMER –
PROGRAMMING EXECUTIVE
COMMUNICATION
Communication Overview
Communication Interface and
Protocol
14 13 12 11
3
P1
Section 8.0 “Programming Executive
4
5
PROGRAMMING
EXECUTIVE SERIAL
TIMING
Figure
6
11
...
7-1).
P2
12
5
13
4
DS70102K-page 21
14
3
P3
Responses”.
15 16
2
1
LSb