DSPIC30F2011-30I/ML Microchip Technology, DSPIC30F2011-30I/ML Datasheet - Page 35

• Manufacturer Part Number: DSPIC30F2011-30I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2011-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DAF30-4 - DEVICE ATP FOR ICE4000
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201130IML

11.2.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGD pin. Once the REGOUT control code is
received, eight clock cycles are required to process the
command. During this time, the CPU is held idle. After
these eight cycles, an additional 16 cycles are required
to clock the data out (see
FIGURE 11-1:
FIGURE 11-2:
FIGURE 11-3:
© 2010 Microchip Technology Inc.
PGC
PGD
PGC
PGD
P2
Execute Previous Instruction,
Fetch REGOUT Control Code
Fetch SIX Control Code
PGD
PGC
Execute PC – 1,
1
0
2
REGOUT SERIAL INSTRUCTION
EXECUTION
0
P3
1
P2
1
3
0
2
1
Execute PC – 1,
Fetch SIX Control Code
0
PGD = Input
4
0
0
3
2
0
0
5
P3
PROGRAM ENTRY AFTER RESET
SIX SERIAL EXECUTION
REGOUT SERIAL EXECUTION
0
4
3
6
0
0
Figure
0
P4
4
7
0
0
1
0
P4
11-3).
8
CPU Held In Idle
2
0
9
LSB X
1
P4
7
LSB X
2
1
P1a
8
P1b
3
X
2
P1B
P5
X
P1A
P1
4
3
X
1
LSb
PGD = Input
X
5
X
P1
4
2
X
1
6
X
5
3
24-bit Instruction Fetch
X
2
PGD = Input
7
X
6
24-bit Instruction Fetch
4
X
3
Shift Out VISI Register <15:0>
8
X
7
The REGOUT instruction is unique because the PGD
pin is an input when the control code is transmitted to
the device. However, once the control code is
processed, the PGD pin becomes an output as the VISI
register is shifted out. After the contents of the VISI are
shifted out, PGD becomes an input again as the state
machine holds the CPU idle until the next 4-bit control
code is shifted in.
5
X
PGD = Output
4
Note:
17
X
8
6
...
X
18 19 20 21 22
17
X
11
X
10
X
18 19 20 21 22
12
X
Once the contents of VISI are shifted out,
the dsPIC
as an output until the first rising edge of
the next clock is received.
11
X
13
X
12
X
14
X
13
X
15 16
®
X
14
X MSB
23 24
DSC device maintains PGD
X MSB
MSb
23 24
P4a
P4a
No Execution Takes Place,
Fetch Next Control Code
1
Execute 24-bit Instruction,
Fetch Next Control Code
Execute 24-bit Instruction,
Fetch Next Control Code
1
PGD = Input
P4a
0
0
DS70102K-page 35
2
2
0
1
0
0
3
3
0
2
0
4
0
4
0
3
0
0
4
0