AT89C51CC01UA-SLSUM Atmel, AT89C51CC01UA-SLSUM Datasheet - Page 80

IC 8051 MCU FLASH 32K 44-PLCC

AT89C51CC01UA-SLSUM

Manufacturer Part Number
AT89C51CC01UA-SLSUM
Description
IC 8051 MCU FLASH 32K 44-PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheet

Specifications of AT89C51CC01UA-SLSUM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
CAN/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
1280 B
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
CANADAPT28
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
1.25KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT89C51CC01UASLSUM

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51CC01UA-SLSUM
Manufacturer:
ATMEL
Quantity:
678
Part Number:
AT89C51CC01UA-SLSUM
Manufacturer:
Atmel
Quantity:
10 000
Figure 43. CAN Controller Block Diagram
CAN Controller Mailbox
and Registers
Organization
80
A/T89C51CC01
TxDC
RxDC
Register
The pagination allows management of the 321 registers including 300(15x20) Bytes of
mailbox via 34 SFR’s.
All actions on the message object window SFRs apply to the corresponding message
object registers pointed by the message object number find in the Page message object
register (CANPAGE) as illustrate in Figure 44.
Page
Timing
Logic
Bit
Interface
Bus
µC-Core Interface
DPR(Mailbox + Registers)
Rec/Tec
Counter
Error
Control
Core
Receive
Stuffing /Destuffing
Redundancy Check
Cyclic
Bit
Transmit
Encoder
Priority
4129N–CAN–03/08

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