AT89C51CC01UA-SLSUM Atmel, AT89C51CC01UA-SLSUM Datasheet - Page 96
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AT89C51CC01UA-SLSUM
Manufacturer Part Number
AT89C51CC01UA-SLSUM
Description
IC 8051 MCU FLASH 32K 44-PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
Specifications of AT89C51CC01UA-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
CAN/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
1280 B
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
CANADAPT28
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
1.25KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT89C51CC01UASLSUM
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51CC01UA-SLSUM
Manufacturer:
ATMEL
Quantity:
678
Registers
96
A/T89C51CC01
Table 58. CANGCON Register
CANGCON (S:ABh)
CAN General Control Register
Reset Value = 0000 0000b
Number
ABRQ
Bit
7
7
6
5
4
3
2
1
0
Bit Mnemonic Description
AUTOBAUD
SYNCTTC
OVRQ
ENA/STB
OVRQ
ABRQ
GRES
TEST
6
TTC
Abort Request
Not an auto-resetable bit. A reset of the ENCH bit (message object control
and DLC register) is done for each message object. The pending transmission
communications are immediately aborted but the on-going communication will
be terminated normally, setting the appropriate status flags, TXOK or RXOK.
Overload frame request (initiator)
Auto-resetable bit.
Set to send an overload frame after the next received message.
Cleared by the hardware at the beginning of transmission of the overload
frame.
Network in Timer Trigger Communication
set to select node in TTC.
clear to disable TTC features.
Synchronization of TTC
When this bit is set the TTC timer is caught on the last bit of the End Of
Frame.
When this bit is clear the TTC timer is caught on the Start Of Frame.
This bit is only used in the TTC mode.
AUTOBAUD
set to active listening mode.
Clear to disable listening mode
Test mode. The test mode is intended for factory testing and not for customer
use.
Enable/Standby CAN Controller
When this bit is set, it enables the CAN controller and its input clock.
When this bit is clear, the on-going communication is terminated normally and
the CAN controller state of the machine is frozen (the ENCH bit of each
message object does not change).
In the standby mode, the transmitter constantly provides a recessive level; the
receiver is not activated and the input clock is stopped in the CAN controller.
During the disable mode, the registers and the mailbox remain accessible.
Note that two clock periods are needed to start the CAN controller state of the
machine.
General Reset (software reset)
Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in
order to reset the controller. After a reset, the controller is disabled.
TTC
5
SYNCTTC
4
AUTOBAUD
3
TEST
2
ENA
1
4129N–CAN–03/08
GRES
0