AT32UC3B0128-A2UT Atmel, AT32UC3B0128-A2UT Datasheet - Page 395
AT32UC3B0128-A2UT
Manufacturer Part Number
AT32UC3B0128-A2UT
Description
IC MCU AVR32 128KB FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0128-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
44
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0128-A2UT
Manufacturer:
XILINX
Quantity:
150
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TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt
Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the
pipe FIFO.
The user then writes into the FIFO (see
DATA)” on page
OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXOUTI shall always be cleared before clearing FIFOCON.
The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write fur-
ther data into the FIFO.
Note that if the user decides to switch to the Suspend state (by writing a zero to the
UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and
the bank is sent.
Figure 22-27. Example of an OUT Pipe with one Data Bank
Figure 22-28. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
SW
SW
write data to CPU
write data to CPU
BANK 0
BANK 0
481) and clears the FIFOCON bit to allow the USBB to send the data. If the
SW
OUT
SW
OUT
SW
(bank 0)
DATA
write data to CPU
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
BANK 1
(bank 0)
DATA
ACK
HW
HW
ACK
SW
OUT
SW
SW
write data to CPU
(bank 1)
DATA
write data to CPU
BANK 0
BANK0
AT32UC3B
ACK
SW
OUT
395
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