AT32UC3B0128-A2UT Atmel, AT32UC3B0128-A2UT Datasheet - Page 439
AT32UC3B0128-A2UT
Manufacturer Part Number
AT32UC3B0128-A2UT
Description
IC MCU AVR32 128KB FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0128-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
44
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0128-A2UT
Manufacturer:
XILINX
Quantity:
150
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• TXINI: Transmitted IN Data Interrupt
32059K–03/2011
Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge
the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple
banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the
next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt
if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.
This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free.
This triggers an EPnINT interrupt if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint
FIFO.
The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is
composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance
with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
AT32UC3B
439
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