AT32UC3B0128-A2UT Atmel, AT32UC3B0128-A2UT Datasheet - Page 74

• Manufacturer Part Number: AT32UC3B0128-A2UT
• Description: IC MCU AVR32 128KB FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0128-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.5.1.3
10.5.1.4
10.5.1.5
32059K–03/2011
RTC interrupt
RTC wakeup
Busy bit
The RTC count value can be read from or written to the Value register (VAL). Due to synchroni-
zation, continuous reading of the VAL register with the lowest prescaler setting will skip every
other value.
The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Reg-
ister (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable
Register (IDR.TOPI). The Interrupt Mask Register (IMR) can be read to see whether or not the
interrupt is enabled. If enabled, an interrupt will be generated if the TOPI bit in the Interrupt Sta-
tus Register (ISR) is set. The TOPI bit in ISR can be cleared by writing a one to the TOPI bit in
the Interrupt Clear Register (ICR.TOPI).
The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static modes.
The RTC can also wake up the CPU directly without triggering an interrupt when the ISR.TOPI
bit is set. In this case, the CPU will continue executing from the instruction following the sleep
instruction.
This direct RTC wake-up is enabled by writing a one to the Wake Enable bit in the CTRL register
(CTRL.WAKEN). When the CPU wakes from sleep, the CTRL.WAKEN bit must be written to
zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction
will have no effect.
The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be
configured independently of the RTC interrupt.
Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values
stored in CTRL, TOP, and VAL to the RTC. The RTC Busy bit in CTRL (CTRL.BUSY) indicates
that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until
the CTRL.BUSY bit goes low again.
AT32UC3B
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