AT32UC3B0128-A2UT Atmel, AT32UC3B0128-A2UT Datasheet - Page 609

• Manufacturer Part Number: AT32UC3B0128-A2UT
• Description: IC MCU AVR32 128KB FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0128-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

27.5.3.4
32059K–03/2011
MEMORY_WORD_ACCESS
Table 27-19. MEMORY_SIZED_ACCESS Details (Continued)
This instruction allows access to the entire Service Access Bus data area. Data is accessed
through the 34 MSB of the SAB address, a direction bit, and 32 bits of data. This instruction is
identical to MEMORY_SIZED_ACCESS except that it always does word sized accesses. The
size field is implied, and the two lowest address bits are removed and not scanned in.
Note: This instruction was previously known as MEMORY_ACCESS, and is provided for back-
wards compatibility.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
Starting in Run-Test/Idle, SAB data is accessed in the following way:
For any operation, the full 34 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 27-20. MEMORY_WORD_ACCESS Details
Instructions
DR output value (Address phase)
DR output value (Data read phase)
DR output value (Data write phase)
Instructions
IR input value
IR output value
DR Size
DR input value (Address phase)
DR input value (Data read phase)
DR input value (Data write phase)
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 34-bit address of the
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a
9. Return to Run-Test/Idle.
data to access.
write operation, scan in the new contents of the area.
Details
xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
xxxxxeb dddddddd dddddddd dddddddd dddddddd
xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Details
10001 (0x11)
peb01
35 bits
aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx
dddddddd dddddddd dddddddd dddddddd xxx
AT32UC3B
609