P89LPC931A1FDH,512 NXP Semiconductors, P89LPC931A1FDH,512 Datasheet - Page 20

• Manufacturer Part Number: P89LPC931A1FDH,512
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC931A1FDH,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288634512

NXP Semiconductors
P89LPC9301_931A1
Product data sheet
Fig 4.
Block diagram of oscillator control
(7.3728 MHz/14.7456 MHz ± 1 %)
WITH CLOCK DOUBLER
7.10 CCLK wake-up delay
7.12 Low power select
7.11 CCLK modification: DIVM register
XTAL1
XTAL2
RC OSCILLATOR
The P89LPC9301/931A1 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles
plus 60 s to 100 s. If the clock source is the internal RC oscillator, the delay is 200 s to
300 s. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
The P89LPC9301/931A1 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the
power consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
(400 kHz ± 5 %)
OSCILLATOR
WATCHDOG
MEDIUM FREQUENCY
HIGH FREQUENCY
LOW FREQUENCY
RCCLK
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 29 November 2010
8-bit microcontroller with accelerated two-clock 80C51 core
TIMER 0 AND
TIMER 1
OSCCLK
DIVM
I
2
C-BUS
CCLK
P89LPC9301/931A1
PCLK
PCLK
÷2
SPI
WDT
CPU
RTC
UART
002aae452
© NXP B.V. 2010. All rights reserved.
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