EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 439
EP9307-IRZ
Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-IRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Company:
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
DMAChArb
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
Address:
30
14
29
13
28
12
0x8000_03C0 - Read/Write
DMA Global Interrupt Register. This register indicates which channels have an
active interrupt. It is a read only register.
RSVD:
D0 - D1:
0x8000_0380 - Read/Write
D[31:12]
Bit No.
Table 10-10. DMA Global Interrupt (DMAGlInt) Register
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
These interrupts are per channel interrupts, as shown in
Table
register per channel. There are no dedicated storage of
these channel interrupts. Once each Channel’s Interrupts’
are clear, the associated channel interrupt is clear.
Note: The order of the internal M2P channel interrupts is
for compatibility reasons with previous versions of
software.
RSVD
24
8
10-10. Each bit is a logical OR of the INTERRUPT
M2M Channel 1 Interrupt
M2M Channel 0 Interrupt
RSVD
M2P Channel 8 Interrupt
M2P Channel 9 Interrupt
M2P Channel 6 Interrupt
M2P Channel 7 Interrupt
M2P Channel 4 Interrupt
M2P Channel 5 Interrupt
M2P Channel 2 Interrupt
M2P Channel 3 Interrupt
M2P Channel 0 Interrupt
M2P Channel 1 Interrupt
Description
23
7
RSVD
22
6
21
5
20
4
19
3
EP93xx User’s Guide
18
2
DMA Controller
17
1
CHARB
10-45
16
0
10
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