EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 541
EP9307-IRZ
Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-IRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Company:
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 541 of 824
- Download datasheet (13Mb)
UART1LinCtrlHigh
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
UART1 Line Control Register High. UART1LinCtrlHigh, UART1LinCtrlMid and
UART1LinCtrlLow form a single 23-bit wide register (UART1LinCtrl) which is updated on a
single write strobe generated by an UART1LinCtrlHigh write. In order to internally update the
contents of UART1LinCtrlMid or UART1LinCtrlLow, a UART1LinCtrlHigh write must always
be performed at the end.
To update the three registers there are two possible sequences:
To update UART1LinCtrlLow or UART1LinCtrlMid only:
30
14
• UART1LinCtrlLow write, UART1LinCtrlMid write and UART1LinCtrlHigh write
• UART1LinCtrlMid write, UART1LinCtrlLow write and UART1LinCtrlHigh write.
• UART1LinCtrlLow write (or UART1LinCtrlMid write) and UART1LinCtrlHigh write.
29
13
28
12
FE:
0x808C_0008 - Read/Write
0x0000_0000
RSVD:
WLEN:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Framing Error. When this bit is set to 1, it indicates that the
received character did not have a valid stop bit (a valid
stop bit is “1”). This bit is cleared to 0 by a write to
UART1RXSts. In FIFO mode, this error is associated with
the character at the top of the FIFO.
Reserved. Unknown During Read.
Number of bits per frame:
11 = 8 bits
10 = 7 bits
01 = 6 bits
00 = 5 bits
24
8
RSVD
23
7
UART1 With HDLC and Modem Control Signals
22
6
WLEN
21
5
FEN
20
4
STP2
19
3
EP93xx User’s Guide
EPS
18
2
PEN
17
1
14-19
BRK
16
0
14
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