ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 187

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

CLOCK CHARACTERISTICS (Cont’d)
12.5.4 PLL Characteristics
Notes:
1. Data characterized but not tested.
2. Under characterization
Figure 101. PLL Jitter vs Signal Frequency
Notes:
1. Measurement conditions: f
Operating conditions: V
V
f
Δ f
OSC
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Voltage Range
PLL input frequency range
PLL jitter
Application Signal Frequency (KHz)
1000
Parameter
1)
DD
CPU
500
3.8 to 5.5V @ T
= 4 MHz, T
250
PLL ON
PLL OFF
A
T
T
f
f
OSC
OSC
= 25°C
A
A
125
= 0 to +70
= -40 to +125
A
= 4 MHz, V
= 2 MHz, V
0 to 70°C
1)
Conditions
°
C
DD
DD
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore, the longer the
period of the application signal, the less it is im-
pacted by the PLL jitter.
Figure 101
plication signals in the range 125 kHz to 2 MHz. At
frequencies of less than 125 kHz, the jitter is neg-
ligible.
1)
°
C
or V
= 4.5 to 5.5V
= 4.5 to 5.5V
DD
4.5 to 5.5V @ T
shows the PLL jitter integrated on ap-
Min
3.8
4.5
2
A
Typ
-40 to 125°C
Note 2
Max
5.5
4
ST72361
187/225
MHz
Unit
%