ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 52

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72361
10 ON-CHIP PERIPHERALS
10.1 WINDOW WATCHDOG (WWDG)
10.1.1 Introduction
The Window Watchdog is used to detect the oc-
currence of a software fault, usually generated by
external interference or by unforeseen logical con-
ditions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the contents of the downcounter before the T6
bit becomes cleared. An MCU reset is also gener-
ated if the 7-bit downcounter value (in the control
register) is refreshed before the downcounter has
reached the window register value. This implies
that the counter must be refreshed in a limited win-
dow.
10.1.2 Main Features
■
■
Figure 34. Watchdog Block Diagram
52/225
– Reset (if watchdog activated) when the down-
– Reset (if watchdog activated) if the down-
Programmable free-running downcounter
Conditional reset
counter value becomes less than 40h
RESET
f
OSC2
MCC/RTC
11
MSB
Write WDGCR
RTC COUNTER
12-BIT MCC
T6:0 > W6:0 CMP
comparator
DIV 64
= 1 when
6
5
LSB
WDGA
-
0
TB[1:0] bits
(MCCSR
Register)
W6
T6
W5
WATCHDOG WINDOW REGISTER (WDGWR)
T5
WATCHDOG CONTROL REGISTER (WDGCR)
■
■
10.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 16384 f
cycles (approx.), and the length of the timeout pe-
riod can be programmed by the user in 64 incre-
ments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit downcounter (T[6:0] bits) rolls
over from 40h to 3Fh (T6 becomes cleared), it ini-
tiates a reset cycle pulling low the reset pin for typ-
ically 30μs. If the software reloads the counter
while the counter is greater than the value stored
in the window register, then a reset is generated.
6-BIT DOWNCOUNTER (CNT)
Hardware/Software
(selectable by option byte)
Optional
(configurable by option byte)
counter is reloaded outside the window (see
Figure
W4
T4
WDG PRESCALER
DIV 4
4)
W3
T3
reset
W2
T2
on
W1
T1
Watchdog
HALT
W0
T0
instruction
activation
OSC2