ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 65

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PWM AUTO-RELOAD TIMER (Cont’d)
Input Capture Function
Input Capture mode allows the measurement of
external signal pulse widths through ARTICRx
registers.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ARTICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ARTICCSR register.
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until the next
read (clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
Figure 45. Input Capture Timing Diagram, f
ICAP SAMPLED
ARTICx PIN
COUNTER
CFx FLAG
f
COUNTER
f
CPU
01h
02h
xxh
ICAP SAMPLED
03h
COUNTER
04h
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
Note: During HALT mode, input capture is inhibit-
ed (the ARTICRx is never reloaded) and only the
external interrupt capability can be used.
Note: The ARTICx signal is synchronized on CPU
clock. It takes two rising edges until ARTICRx is
latched with the counter value. Depending on the
prescaler value and the time when the ICAP event
occurs, the value loaded in the ARTICRx register
may be different.
If the counter is clocked with the CPU clock, the
value latched in ARTICRx is always the next coun-
ter value after the event on ARTICx occurred
ure
If the counter clock is prescaled, it depends on the
position of the ARTICx event within the counter cy-
cle
= f
(Figure
CPU
45).
05h
46).
COUNTER
06h
).
05h
INTERRUPT
07h
ST72361
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t
(Fig-