ST72F63BK4M1 STMicroelectronics, ST72F63BK4M1 Datasheet - Page 114
![IC MCU 8BIT LS 16K 34-SOIC](/photos/12/15/121510/497-34-soic_series_sml.jpg)
ST72F63BK4M1
Manufacturer Part Number
ST72F63BK4M1
Description
IC MCU 8BIT LS 16K 34-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK4M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SCI, USB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
2 x 16 bit
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-2115-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F63BK4M1
Manufacturer:
ST
Quantity:
20 000
On-chip peripherals
Note:
114/186
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In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF
flags that are set at the same time. It is then necessary to release both lines by software.
each 9-bit transaction:
Single Master mode
If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the
BERR flag will not be set and transfer will continue however the BUSY flag will be reset.
To work around this, slave devices should issue a NACK when they receive a
misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle
of communication gives the possibility to reinitiate transmission.
Multimaster mode
Normally the BERR bit would be set whenever unauthorized transmission takes place
while transfer is already in progress. However, an issue will arise if an external master
generates an unauthorized Start or Stop while the I
pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit
during I
handled in a similar manner as the BERR flag being set.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
2
C master mode transmission. The resetting of the BUSY bit can then be
Doc ID 7516 Rev 8
2
C master is on the first or second
ST7263Bxx