MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 259
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.5.3.2
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors.
The protection logic implements the following features:
12.5.3.3
Figure 12-42
The clock source bit (CLKSRC) in the CANCTL1 register (12.3.2/-226) defines whether the internal
CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock.
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the
CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the
clock is required.
Freescale Semiconductor
•
•
•
•
The receive and transmit error counters cannot be written or otherwise manipulated.
All registers which control the configuration of the MSCAN cannot be modified while the MSCAN
is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK
handshake bits in the CANCTL0/CANCTL1 registers (see
Register 0
— MSCAN control 1 register (CANCTL1)
— MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1)
— MSCAN identifier acceptance control register (CANIDAC)
— MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7)
— MSCAN identifier mask registers (CANIDMR0–CANIDMR7)
The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power
down mode or initialization mode (see
Section 12.5.5.5, “MSCAN Initialization
The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which
provides further protection against inadvertently disabling the MSCAN.
Oscillator Clock
Bus Clock
Protocol Violation Protection
Clock System
shows the structure of the MSCAN clock generation circuitry.
(CANCTL0)”) serve as a lock to protect the following registers:
Figure 12-42. MSCAN Clocking Scheme
MC9S08DZ60 Series Data Sheet, Rev. 4
CLKSRC
Section 12.5.5.6, “MSCAN Power Down
Mode”).
CANCLK
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MSCAN
CLKSRC
Prescaler
(1 .. 64)
Section 12.3.1, “MSCAN Control
Time quanta clock (Tq)
Mode,” and
259
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