MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 398

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MC9S12XET256CAG

Manufacturer Part Number
MC9S12XET256CAG
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XET256CAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XET256CAG
Manufacturer:
FREESCALE
Quantity:
1 701
Part Number:
MC9S12XET256CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XET256CAG
Manufacturer:
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Chapter 10 XGATE (S12XGATEV3)
ASR
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift
for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
398
N:
Z:
V:
C:
ASR RD, #IMM4
ASR RD, RS
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Z
old
V
Source Form
^ RD[15]
C
new
MC9S12XE-Family Reference Manual , Rev. 1.23
Address
b15
Mode
IMM4
DYA
Arithmetic Shift Right
0
0
0
0
RD
n
0
0
0
0
1
1
Machine Code
RD
RD
C
RS
IMM4
1
1
0
Freescale Semiconductor
0
0
ASR
0
0
1
1
Cycles
P
P

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