MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 869

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.4.2
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see
Freescale Semiconductor
FCMD
0x0D
•
•
•
0x0B
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x20
Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
Writing an invalid command as part of the command write sequence
For additional possible errors, refer to the error handling table provided for each command
Flash Command Description
Disable EEPROM
Program D-Flash
Enable EEPROM
Emulation Query
Partition D-Flash
Set User Margin
Set Field Margin
Unsecure Flash
Full Partition D-
Erase Verify D-
Erase D-Flash
Flash Section
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
Command
Emulation
Emulation
EEPROM
Sector
Flash
Level
Level
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
Specifies a user margin read level for the D-Flash block.
Specifies a field margin read level for the D-Flash block (special modes only).
Erase the D-Flash block and partition an area of the D-Flash block for user access.
Verify that a given number of words starting at the address provided are erased.
Program up to four words in the D-Flash block.
Erase all bytes in a sector of the D-Flash block.
Enable EEPROM emulation where writes to the buffer RAM EEE partition will be copied
to the D-Flash EEE partition.
Suspend all current erase and program activity related to EEPROM emulation but leave
current EEE tags set.
Returns EEE partition and status variables.
Partition an area of the D-Flash block for user access.
MC9S12XE-Family Reference Manual , Rev. 1.23
Section
Table 24-32. D-Flash Commands
24.3.2.7).
CAUTION
Function on D-Flash Memory
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
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