MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 492

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
The Sequence for clock quality check is shown in
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
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POR
LVR
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset
check the OSCCLK signal.
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (f
during Pseudo Stop Mode.
CHECK WINDOW
CLOCK OK
OSC OK
ACTIVE?
NUM = 50
SCM
?
YES
NO
FSTWKP=1
SCME=1 &
NO
?
EXIT FULL STOP
NO
YES
Figure 11-18. Sequence for Clock Quality Check
CM FAIL
MC9S12XE-Family Reference Manual , Rev. 1.23
YES
1
SWITCH TO OSCCLK
handling the clock quality checker continues to
NUM = NUM-1
NUM = 0
EXIT SCM
NUM > 0
?
YES
NOTE
NOTE
Figure
NO
CLOCK MONITOR RESET
11-18.
ENTER SCM
ENTER SCM
YES
SCM
) and an active VREG
SCME = 1
ACTIVE?
SCM
?
NO
YES
FSTWKP = 0
NO
YES
?
Freescale Semiconductor
NO
NUM = 0