R5F21266SNFP#U0 Renesas Electronics America, R5F21266SNFP#U0 Datasheet - Page 238
![IC R8C/26 MCU FLASH 32LQFP](/photos/12/37/123707/r5f21266snfp_u0_sml.jpg)
R5F21266SNFP#U0
Manufacturer Part Number
R5F21266SNFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21266SNFP#U0
Core Size
16/32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
R8C
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
25
Ram Memory Size
1.5KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
2.2V To 5.5V
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 14.58
TRCGRB register
TRCGRD register
TRCCR2 register
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TRCTRG input
TSTART bit in
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
CSEL bit in
IMFA bit in
IMFB bit in
IMFC bit in
TRCGRB register).
Count source
Sep 26, 2008
FFFFh
TRC register value
0000h
m
n
p
1
0
1
0
1
0
1
0
1
0
Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
“L” initial output
n
“H” output at
TRCGRC register
compare match
Transfer from buffer register to general register
Page 219 of 453
n+1
p+1
Count starts
when TSTART
bit is set to 1
Transfer
“L” output at
TRCGRB register
compare match
n
Set to 0 by
a program
n
Inactive level so
TRCTRG input is
enabled
Previous value
TSTART bit is
p+1
TRC register (counter)
cleared at TRCTRG pin
trigger input
Changed by a program
held if the
Transfer
set to 0
Return to initial value if the
TSTART bit is set to 0
n
Set to 0 by
a program
Set to 1 by
a program
Transfer from buffer register to general register
Set to 0000h
by a program
m+1
n+1
p+1
Transfer
Active level so TRCTRG
input is disabled
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
Count starts at
TRCTRG pin
trigger input
n
Set to 0 by
a program
Next data
TRC register cleared
at TRCGRA register
compare match
Set to 0 by
a program
Count stops
because the
CSEL bit is
set to 1
The TSTART
bit is set to 0
Transfer
14. Timers
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