R5F21266SNFP#U0 Renesas Electronics America, R5F21266SNFP#U0 Datasheet - Page 304
![IC R8C/26 MCU FLASH 32LQFP](/photos/12/37/123707/r5f21266snfp_u0_sml.jpg)
R5F21266SNFP#U0
Manufacturer Part Number
R5F21266SNFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21266SNFP#U0
Core Size
16/32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
R8C
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
25
Ram Memory Size
1.5KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
2.2V To 5.5V
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (5Mb)
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.19
TDRE bit in
SSSR register
TEND bit in
SSSR register
TDRE bit in
SSSR register
TEND bit in
SSSR register
Processing
by program
Processing
by program
Sep 26, 2008
• CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops)
• CPHS bit = 1 (data change at even edges) and CPOS bit = 0 (“H” when clock stops)
(output)
(output)
SSCK
SSCK
SSO
Transmission (4-Wire Bus Communication Mode)
SSO
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
SCS
SCS
1
0
1
0
1
0
1
0
CPHS, CPOS: Bits in SSMR register
Data write to SSTDR register
Data write to SSTDR register
TXI interrupt request
is generated
TXI interrupt request
is generated
Page 285 of 453
b7
b7
1 frame
b6
1 frame
b6
b0
TXI interrupt request
is generated
TXI interrupt request
is generated
b0
b7
1 frame
b7
b6
TEI interrupt request is
generated
TEI interrupt request is
generated
1 frame
16. Clock Synchronous Serial Interface
b6
b0
b0
High-impedance
High-impedance
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