C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 157
C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F045-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
EA
Bit7
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
ET2: Enabler Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2 flag.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
IEGF0
R/W
Bit6
SFR Definition 12.11. IE: Interrupt Enable
ET2
R/W
Bit5
ES0
R/W
Bit4
Rev. 1.5
ET1
R/W
Bit3
C8051F040/1/2/3/4/5/6/7
EX1
R/W
Bit2
ET0
R/W
Bit1
SFR Address:
SFR Page:
EX0
R/W
Bit0
0xA8
All Pages
00000000
Addressable
Reset Value
Bit
157
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