C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 324
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C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F045-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F040/1/2/3/4/5/6/7
322
This register determines how the Flash interface logic will respond to reads and writes to the
Bit 7:
Bits6-4:
Bits3-0:
SFLE
Bit7
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control Register
FLASHDAT Register.
SFLE: Scratchpad Flash Memory Access Enable
When this bit is set, Flash reads and writes from user software are directed to the 128-byte
scratchpad Flash sector. When accessing the scratchpad, Flash accesses out of the
address range 0x00-0x7F should not be attempted. Reads/Writes outside of this range will
yield undefined results.
0: Flash access is directed to the Program/Data Flash sector.
1: Flash access is directed to the 128-byte scratchpad sector.
WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
000:
001:
010:
(All other values for WRMD2-0 are reserved.)
RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-
DAT Register per the following values:
0000:
0001:
0010:
(All other values for RDMD3-0 are reserved.)
WRMD2
Bit6
A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. The data written must be 0xA5 for the erase
to occur. FLASHADR is not affected. If FLASHADR targets the Read Lock Byte or
the Write/Erase Lock Byte, the entire user space will be erased (i.e. entire Flash
memory except for the Reserved area (See
page
A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR regis-
ter if no operation is currently active. This mode is used for block reads.
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
WRMD1
179).
Bit5
WRMD0
Bit4
RDMD3
Rev. 1.5
Bit3
RDMD2
Bit2
Section “15. Flash Memory” on
RDMD1
Bit1
RDMD0
Bit0
00000000
Reset Value
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