C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 319
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C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F045-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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25. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-
tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully
compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-
ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the seven instructions shown in Figure 25.1 can
be commanded. There are three DRs associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084 Flash Address Selects FLASHADR Register which holds the address of all Flash read,
Value
Bit15
IR
Flash Control
JTAG Register Definition 25.1. IR: JTAG Instruction Register
Instruction
Flash Data
PRELOAD
SAMPLE/
EXTEST
IDCODE
BYPASS
Selects the Boundary Data Register for observability and presetting the
Selects the Boundary Data Register for control and observability of all
device pins
scan-path latches
Selects device ID Register (DEVICEID)
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds
to reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
write, and erase operations
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Description
Bit0
Reset Value
0x0000
317
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