C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 321
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C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F045-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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25.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all
the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
25.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of
the scan-path latches.
25.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-
ister.
25.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
75, 77, 79, 81, 83,
85, 87, 89
90, 92, 94, 96, 98,
100, 102, 104
91, 93, 95, 97, 99,
101, 103, 105
106, 108, 110, 112,
114, 116, 118, 120
107, 109, 111, 113,
115, 117, 119, 121
122, 124, 126, 128,
130, 132, 134, 136
123, 125, 127, 129,
131, 133, 135, 137
Table 25.1. Boundary Data Register Bit Definitions (Continued)
Capture P4.n input from pin
Update
Capture P5.n output enable from MCU
Update
Capture P5.n input from pin
Update
Capture P6.n output enable from MCU
Update
Capture P6.n input from pin
Update
Capture P7.n output enable from MCU
Update
Capture P7.n input from pin
Update
Action
Target
P4.n output to pin
P5.n output enable to pin
P5.n output to pin
P6.n output enable to pin
P6.n output to pin
P7.n output enable to pin
P7.n output to pin
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
319
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