C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 182
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C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F045-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F040/1/2/3/4/5/6/7
The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the
block containing the security bytes. This allows additional blocks to be protected after the block containing
the security bytes has been locked. Important Note: The only means of removing a lock once set is to
erase the entire program memory space by performing a JTAG erase operation (i.e., cannot be
done in user firmware). Addressing either security byte while performing a JTAG erase operation
will automatically initiate erasure of the entire program memory space (except for the reserved
area). This erasure can only be performed via JTAG. If a non-security byte in the 0xFBFF-0xFDFF
(C8051F040/1/2/3/4/5) or 0x7DFF-0x7FFF (C8051F046/7) page is addressed during the JTAG era-
sure, only that page (including the security bytes) will be erased.
The Flash Access Limit security feature (see Figure 15.1) protects proprietary program code and data from
being read by software running on the C8051F04x. This feature provides support for OEMs that wish to
program the MCU with proprietary value-added firmware before distribution. The value-added firmware
can be protected while allowing additional code to be programmed in remaining program memory space
later.
The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program
memory space. The first is an upper partition consisting of all the program memory locations at or above
the SRL address, and the second is a lower partition consisting of all the program memory locations start-
ing at 0x0000 up to (but excluding) the SRL address. Software in the upper partition can execute code in
the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc-
tion. (Executing a MOVC instruction from the upper partition with a source address in the lower partition
will always return a data value of 0x00.) Software running in the lower partition can access locations in both
the upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-
added firmware via the reset vector. Once the value-added firmware completes its initial execution, it
branches to a predetermined location in the upper partition. If entry points are published, software running
in the upper partition may execute program code in the lower partition, but it cannot read the contents of
the lower partition. Parameters may be passed to the program code running in the lower partition either
through the typical method of placing them on the stack or in registers before the call or by placing them in
prescribed memory locations in the upper partition.
The SRL address is specified using the contents of the Flash Access Register. The 16-bit SRL address is
calculated as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be
located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase sector
size essentially requires that a 512 boundary be used. The contents of a non-initialized SRL security byte
is 0x00, thereby setting the SRL address to 0x0000 and allowing read access to all locations in program
memory space by default.
182
Rev. 1.5
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