C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 239
C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F045-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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19. System Management BUS/I
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System
Management Bus Specification, version 2, and compatible with the I
interface by the system controller are byte oriented with the SMBus0 interface autonomously controlling
the serial transfer of the data. A method of extending the clock-low duration is available to accommodate
devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation. SMBus0 is controlled by SFRs as described in
page
SMBUS
IRQ
245.
S
L
V
6
S
L
V
5
SMB0ADR
S
L
V
4
B
U
S
Y
Interrupt
Request
B
S
L
V
3
M
E
N
S
B
7
S
L
V
2
SMB0CN
S
T
A
A
S
L
V
1
O
S
T
S
L
V
0
S
I
G
C
A
A
F
T
E
B
O
T
E
SFR Bus
0000000b
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
A
7 MSBs
S
A
T
7
Figure 19.1. SMBus0 Block Diagram
S
A
SFR Bus
T
6
SMB0STA
S
T
A
5
S
T
A
4
8
S
T
A
3
SMB0DAT
S
T
A
2
Read
S
T
A
1
7
S
T
A
0
6
8
SMB0DAT
5
4
C
R
7
3
C
R
6
Clock Divide
Data Path
8
2
Control
2
SMB0CR
C
R
5
C BUS (SMBUS0)
Logic
1
SMB0DAT
Rev. 1.5
C
R
4
Write to
0
C
R
3
C
R
2
C
R
1
Control
C8051F040/1/2/3/4/5/6/7
C
R
0
SDA
Control
SCL
1
0
SYSCLK
FILTER
FILTER
2
C serial bus. Reads and writes to the
N
N
SDA
SCL
C
R
O
R
S
S
B
A
Section 19.4 on
Port I/O
239
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