HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet
HD6417011VX20V
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HD6417011VX20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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SH7011 32 Hardware Manual Rev.1.0 1998.12 ...
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Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with ...
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Section 1 SH7011 Overview 1.1 SH7011 Overview ............................................................................................................. 1.1.1 SH7011 Features .................................................................................................. 1.2 Block Diagram................................................................................................................... 1.3 Pin Arrangement and Pin Functions.................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ Section 2 CPU ..................................................................................................................... 2.1 Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn) ...
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Section 5 Exception Processing 5.1 Overview............................................................................................................................ 45 5.1.1 Types of Exception Processing and Priority ........................................................ 45 5.1.2 Exception Processing Operations ......................................................................... 46 5.1.3 Exception Processing Vector Table...................................................................... 47 5.2 Resets................................................................................................................................. 49 5.2.1 Reset ..................................................................................................................... 49 5.2.2 Power-On Reset.................................................................................................... 49 5.3 ...
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Stack after Interrupt Exception Processing .......................................................... 70 6.5 Interrupt Response Time.................................................................................................... 70 Section 7 Bus State Controller (BSC) 7.1 Overview............................................................................................................................ 73 7.1.1 Features ................................................................................................................ 73 7.1.2 Block Diagram...................................................................................................... 74 7.1.3 Pin Configuration ................................................................................................. 75 7.1.4 Register Configuration ......................................................................................... 75 ...
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Basic Functions .................................................................................................... 116 8.4.3 Synchronous Operation ........................................................................................ 122 8.4.4 Buffer Operation .................................................................................................. 124 8.4.5 Cascade Connection Mode ................................................................................... 127 8.4.6 PWM Mode .......................................................................................................... 128 8.5 Interrupts............................................................................................................................ 133 8.5.1 Interrupt Sources and Priority Ranking................................................................ 133 8.5.2 A/D Converter Activation ...
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Timer 2 Constant Register (T2COR) ................................................................... 175 10.3 Operation ........................................................................................................................... 176 10.3.1 Cyclic Count Operation........................................................................................ 176 10.3.2 T2CNT Count Timing.......................................................................................... 176 10.4 Interrupts............................................................................................................................ 177 10.4.1 Interrupt Source.................................................................................................... 177 10.4.2 Timing of Compare Match Flag Setting .............................................................. 177 10.4.3 Timing ...
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Serial Control Register (SCR).............................................................................. 197 12.2.7 Serial Status Register (SSR)................................................................................. 199 12.2.8 Bit Rate Register (BRR)....................................................................................... 203 12.3 Operation ........................................................................................................................... 211 12.3.1 Overview .............................................................................................................. 211 12.3.2 Operation in Asynchronous Mode........................................................................ 212 12.3.3 Multiprocessor Communication ........................................................................... 221 12.4 Interrupt ............................................................................................................................. ...
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Port A Data Register H (PADRH)........................................................................ 256 15.3 Port E ................................................................................................................................. 257 15.3.1 Register Configuration ......................................................................................... 257 15.3.2 Port E Data Register (PEDR) ............................................................................... 258 Section 16 RAM ................................................................................................................... 261 16.1 Overview............................................................................................................................ 261 Section 17 Electrical Characteristics 17.1 Absolute ...
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Section 1 SH7011 Overview 1.1 SH7011 Overview The SH7011 CMOS single-chip microprocessors integrate a Hitachi-original architecture, high- speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set Most instructions can be executed in one ...
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Interrupt Controller (INTC): Nine external interrupt pins (NMI, IRQ0 to IRQ7) Twenty-two internal interrupt sources Sixteen programmable priority levels Bus State Controller (BSC): Supports external extended memory access 16-bit external data bus Memory address space divided into four areas (four ...
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Serial Communication Interface (SCI) (One Channel): Asynchronous mode Can transmit and receive simultaneously (full duplex) On-chip dedicated baud rate generator Multiprocessor communication function I/O Ports: Input/output: 11 A/D Converter: 10 bits 7 channels Sample & hold function Large Capacity On-Chip ...
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Block Diagram RES EXTAL XTAL Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss : Peripheral address bus : Peripheral data bus : Internal address bus : Internal ...
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Pin Arrangement and Pin Functions 1.3.1 Pin Arrangment CK 76 RES 77 PE0/TIOC0A 78 PE2/TIOC0C 79 Vcc 80 PE4/TIOC1A 81 PE5/TIOC1B 82 PE6/TIOC2A 83 Vss 84 AN0 85 AN1 86 AN2 87 AN3 88 AN4 89 AN5 90 AVss ...
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Pin Functions Table 1.1 lists the pin functions. Table 1.1 Pin Functions Classification Symbol Power supply Clock EXTAL XTAL CK RES System control Interrupts NMI IRQ0–IRQ7 I Address bus A1–A21 Data bus D0–D15 CS0 to ...
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Table 1.1 Pin Functions (cont) Classification Symbol Multifunction TIOC0A timer/pulse unit TIOC0C (MTU) TIOC1A TIOC1B TIOC2A TIOC2B Serial TxD communication interface (SCI) RxD A/D Converter AN0 to AN6 I I/O ports PA18, 19 PE0 ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for data ...
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Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the ...
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System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and ...
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Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded into a ...
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Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 Instruction ...
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Table 2.3 Delayed Branch Instructions SH7011 CPU BRA TRGET ADD R1,R0 Multiplication/Accumulation Operation: 16-bit executed in one to two cycles. 16-bit 16-bit + 64-bit operations are executed in two to three cycles. 32-bit 64-bit multiplication/accumulation operations are executed in two ...
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Table 2.5 Immediate Data Accessing Classification SH7011 CPU 8-bit immediate MOV 16-bit immediate MOV.W .DATA.W 32-bit immediate MOV.L .DATA.L Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the ...
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Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Direct register Rn addressing Indirect register @Rn addressing Post-increment @Rn+ indirect register addressing Pre-decrement @–Rn indirect register ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Indirect register @(disp:4, addressing with Rn) displacement Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register addressing Indirect GBR @(disp:8, addressing with GBR) ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR addressing PC relative @(disp:8, addressing with PC) displacement 18 Effective Addresses Calculation GBR ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format PC relative disp:8 addressing disp:12 Rn Immediate #imm:8 addressing #imm:8 #imm:8 Effective Addresses Calculation The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, ...
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Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: xxxx: Instruction code mmmm: Source register nnnn: ...
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Table 2.9 Instruction Formats (cont) Instruction Formats nm format 15 xxxx nnnn xxxx mmmm md format 15 xxxx xxxx dddd mmmm nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx nnnn mmmm dddd Note: In multiply/accumulate instructions, nnnn ...
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Table 2.9 Instruction Formats (cont) Instruction Formats d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx ...
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Instruction Set by Classification Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operations ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL ...
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Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP ...
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Table 2.10 Classification of Instructions (cont) Operation Classification Types Code System 11 CLRT control CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction ...
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Table 2.11 Instruction Code Format Item Format Instruction OP.Sz SRC,DEST Instruction MSB LSB code Operation , (xx) M/Q/T & <<n >>n Execution — cycles T bit — Notes: 1. Depending on the operand size, displacement is scaled ...
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Table 2.12 Data Transfer Instructions Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) ...
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Table 2.12 Data Transfer Instructions (cont) Instruction MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) MOV.W R0,@(disp,GBR) MOV.L R0,@(disp,GBR) MOV.B @(disp,GBR),R0 MOV.W @(disp,GBR),R0 MOV.L @(disp,GBR),R0 MOVA @(disp,PC),R0 MOVT Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn 28 ...
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Table 2.13 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL Rn ...
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Table 2.13 Arithmetic Operation Instructions (cont) Instruction Instruction Code DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W ...
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Table 2.13 Arithmetic Operation Instructions (cont) Instruction Instruction Code SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Note: The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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Table 2.16 Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 Note: ...
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Table 2.17 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L ...
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Table 2.17 System Control Instructions (cont) Instruction Instruction Code STS.L MACH,@–Rn 0100nnnn00000010 STS.L MACL,@–Rn 0100nnnn00010010 STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Note: The number of execution cycles before the chip enters sleep mode. Operation Rn–4 Rn, MACH (Rn) Rn–4 Rn, ...
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Processing States 2.5.1 State Transitions The CPU has four processing states: reset, exception processing, program execution and power- down. Figure 2.6 shows the transitions between the states. From only state when RES = 0 Reset states Sleep mode Figure ...
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For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of ...
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Section 3 Power-Down State 3.1 Overview In the power-down state, CPU functions are halted, greatly reducing the power consumption of the chip. 3.1.1 Power-Down State The power-down state consists of a sleep mode. Table 3.1 shows the conditions for entering ...
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Sleep Mode 3.2.1 Transition to Sleep Mode When the SLEEP instruction is executed, the chip makes a transition from the program execution state to sleep mode. Immediately after execution of the SLEEP instruction the CPU halts, but the contents ...
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Section 4 Clock Pulse Generator (CPG) 4.1 Overview The clock pulse generator (CPG) supplies clock pulses within the SH7011 and to external devices. The SH7011’s CPG operates the SH7011 at a frequency equal to the oscillation frequency of the crystal ...
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EXTAL XTAL Figure 4.2 Example of Crystal Resonator Connection Table 4.1 Damping Resistance Value Frequency (MHz Crystal Resonator: Figure 4.3 shows an equivalent circuit for the crystal resonator. Use a crystal resonator with the characteristics shown in table ...
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External Clock Input Input the external clock to the EXTAL pin and leave the XTAL pin open (figure 4.4.). The external clock frequency should be the same as that of the system clock (CK). XTAL EXTAL 4.3 Usage Notes ...
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Notes on Duty Adjustment: Duty adjustment circuit is performed on an input clock of 5 MHz or higher. With a frequency of less than 5 MHz, duty adjustment may not be performed, but AC characteristics t (clock high-level width) and ...
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Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur ...
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Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and the Start of Exception Processing Exception Source Power-on reset Address error ...
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Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the ...
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Table 5.3 Exception Processing Vector Table (cont) Exception Sources Interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 On-chip peripheral module* Note: The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section ...
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Resets 5.2.1 Reset A reset has the highest priority of any exception source. As shown in table 5.5, a power-on reset initializes the internal state of the CPU and the on-chip peripheral module registers. Table 5.5 Types of Resets ...
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Address Errors Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Cycle Description Instruction fetch Instruction fetched from even address ...
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Interrupts Table 5.7 shows the sources that start up interrupt exception processing. These are divided into NMI, IRQ and on-chip peripheral modules. Table 5.7 Interrupt Sources Type NMI IRQ On-chip peripheral module Each interrupt source is allocated a different ...
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Table 5.8 Interrupt Priority Order Type NMI IRQ On-chip peripheral module 5.4.2 Interrupt Exception Processing When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if ...
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Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. ...
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When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction sometimes not accepted immediately but stored instead, as shown in table 5.10. When this ...
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Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.11. Table 5.11 Types of Stack Status After Exception Processing Ends Types Address error Trap instruction General illegal instruction ...
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Notes on Use 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed during exception processing. ...
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Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by ...
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Block Diagram Figure 6 block diagram of the INTC. NMI IRQ0 IRQ1 IRQ2 Input IRQ3 control IRQ4 IRQ5 IRQ6 IRQ7 (Interrupt request) MTU (Interrupt request) CMT (Interrupt request) SCI (Interrupt request) A/D (Interrupt request) TIM1 (Interrupt request) ...
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Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Non-maskable interrupt input pin Interrupt request input pins 6.1.4 Register Configuration The INTC has the 10 registers shown in table 6.2. These registers set the ...
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Interrupt Sources There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving ...
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On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: Multifunction timer pulse unit (MTU) Compare match timer (CMT) Serial communications interface (SCI) A/D converter (A/D) 8-bit timer 1 (TIM1) 8-bit timer ...
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Table 6.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Vector Interrupt Source No. NMI 11 IRQ0 64 IRQ1 65 IRQ2 66 IRQ3 67 IRQ4 68 IRQ5 69 IRQ6 70 IRQ7 71 MTU0 TGI0A 88 TGI0B 89 TGI0C 90 TGI0D ...
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Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Interrupt Source No. MTU1 TGI1A 96 TGI1B 97 TCI1V 100 MTU2 TGI2A 104 TGI2B 105 TCI2V 108 SCI ERI 132 RXI 133 TXI 134 TEI 135 A/D ADI ...
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Description of Registers 6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set priority levels from for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources ...
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IPRA–IPRH are initialized to H'0000 by a power-on reset. Reserved bits always return 0 if read, and the write value for these bits should always be 0. 6.3.2 Interrupt Control Register (ICR) The ICR is a 16-bit register that sets ...
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Bits 7 to 0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7 interrupt request detection mode. Bits 7-0: IRQ0S–IRQ7S Description 0 Interrupt request is detected on low level of IRQ input (initial value) 1 Interrupt request is detected on falling ...
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Bits 7 to 0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt request status. Bits 7-0: IRQ0F–IRQ7F Detection Setting 0 Level detection Edge detection 1 Level detection Edge detection Level IRQ pin detection Edge detection RESIRQn (IRQn interrupt acceptance/IRQnF = ...
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Interrupt Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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Program execution state No Interrupt? Yes No NMI? Yes Yes Save SR to stack Save PC to stack Copy accept-interrupt level Reads exception vector table Branches to exception service routine I3 to I0: Interrupt mask bits ...
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Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always be certain that SP ...
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Table 6.5 Interrupt Response Time NMI, Peripheral Item Module Compare identified inter rupt priority with SR mask level Wait for completion sequence currently being executed by CPU Time from start of interrupt 5 ...
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Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation ...
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Section 7 Bus State Controller (BSC) 7.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM, and ROM to be linked directly to the LSI ...
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Block Diagram Figure 7.1 shows the BSC block diagram. WAIT control unit CS0–CS3 control unit RD control unit WRH, WRL WCR1: Wait control register 1 BCR2: Bus control register 2 74 WCR1 Wait Area BCR2 Memory BSC Figure 7.1 ...
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Pin Configuration Table 7.1 shows the bus state controller pin configuration. Table 7.1 Pin Configuration Pin Name I/O A21–A1 Output D15–D0 I/O CS0–CS3 Output RD Output WRH Output WRL Output WAIT Input 7.1.4 Register Configuration The bus state controller ...
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Address Map Figure 7.2 shows the address format used by the SH7092. A31–A24 A23, A22 Space selection: Not output externally; used to select the type of space Reserved (do not access) when 00000010 to 11111110 (H'01 to H'FE) On-chip ...
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Description of Registers 7.2.1 Bus Control Register 2 (BCR2) BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized by power-on resets to H'FFFF. ...
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Bit 13 (IW21) Bit 12 (IW20 Bit 11 (IW11) Bit 10 (IW10 Bit 9 (IW01) Bit 8 (IW00 Bits 7–4—Idle Specification for ...
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Bit 5 (CW1) Description 0 No CS1 space continuous access idle cycles 1 One CS1 space continuous access idle cycle (initial value) Bit 4 (CW0) Description 0 No CS0 space continuous access idle cycles 1 One CS0 space continuous access ...
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Wait Control Register 1 (WCR1) Wait control register 1 (WCR1 16-bit read/write register that specifies the number of wait cycles (0-3) for each CS space. WCR1 is initialized to H'FFFF by power-on resets. Bit: 15 — Initial ...
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Bits 7 and 6—Reserved. These bits always read 1. The write value should always be 1. Bits 5 and 4—CS1 Space Wait Specification (W11, W10): These bits specify the number of waits for CS1 space accesses. Bit 5 (W11) Bit ...
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Accessing Ordinary Space A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 7.3.1 Basic Timing Figure 7.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are ...
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Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR settings. The specified number of T with the timing shown in figure 7.4. CK Address CSn RD Read Data ...
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When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 7.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise ...
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CS Assert Period Extension 7.3.3 Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This allows ...
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Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the ...
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IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this LSI write accesses. In the same manner, IW21 and IW20 specify the number of ...
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Memory Connection Examples Figure 7.9 16-Bit Data Bus Width ROM Connection SH7011 Figure 7.10 16-Bit Data Bus Width SRAM Connection 88 256k SH7011 CE CSn RD OE A1–A18 A0–A17 I/O0–I/O15 D0–D15 128k SRAM CSn A1–A17 A0–A16 ...
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Section 8 Multifunction Timer Pulse Unit (MTU) 8.1 Overview The SH microprocessor has an on-chip 16-bit multifunction timer pulse unit (MTU) with three channels of 16-bit timers. 8.1.1 Features Can process a maximum of six different pulse outputs and inputs. ...
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Channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. A/D converter conversion start trigger can be generated Channel compare-match/input capture signals can be used as ...
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Table 8.1 summarizes the MTU functions. Table 8.1 MTU Functions Item Channel 0 Counter clocks Internal: Six to each channel General registers TGR0A TGR0B General TGR0C registers/buffer TGR0D registers Input/output pins TIOC0A TIOC0C Counter clear TGR compare-match or function input ...
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Block Diagram Figure 8.1 is the block diagram of the MTU. [Clock input] Internal clock /16 /64 /256 /1024 [I/O pins] Channel 0: TIOC0A TIOC0C Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B 92 Figure 8.1 MTU ...
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Pin Configuration Table 8.2 summarizes the MTU pins. Table 8.2 Pin Configuration Channel Name 0 Input capture/output compare-match 0A Input capture/output compare-match 0C 1 Input capture/output compare-match 1A Input capture/output compare-match 1B 2 Input capture/output compare-match 2A Input capture/output ...
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Register Configuration Table 8.3 summarizes the MTU register configuration. Table 8.3 Register Configuration Chan- nel Name Shared Timer start register Timer synchro register 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H TIOR0H R/W ...
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Table 8.3 Register Configuration (cont) Chan- nel Name 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 General register 2A General register 2B ...
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Bits 7–5—Counter Clear (CCLR2, CCLR1, CCLR0): Select the counter clear source for the TCNT counter. Channels 0: Bit 7: Bit 6: Bit 5: CCLR2 CCLR1 CCLR0 ...
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Bit 4: Bit 3: CKEG1 CKEG0 Description 0 0 Count on rising edges (initial value) 1 Count on falling edges 1 X Count on both rising and falling edges Notes don’t care. 2. Internal clock ...
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Channel 1: Bit 2: Bit 1: Bit 0: TPSC2 TPSC1 TPSC0 Channel 2: Bit 2: Bit 1: Bit 0: TPSC2 TPSC1 TPSC0 ...
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Timer Mode Register (TMDR) The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU has three TMDR registers, one for each channel. TMDR is initialized to H' power-on reset. Channel ...
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Bits 3–0—Modes 3–0 (MD3–MD0): These bits set the timer operation mode. Bit 3: Bit 2: Bit 1: Bit 0: MD3 MD2 MD1 MD0 ...
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Channel 0: TIOR0L Bit: 7 — Initial value: 0 R/W: R Note: When the TGRC or TGRD registers are set for buffer operation, these settings become ineffective and the operation buffer register. Bits 7–4—Reserved. These bits always ...
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Channel 0 (TIOR0L Register): Bits 7–4—Reserved. These bits always read 0. The write value should always be 0. Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR0C register function. Bit 3: Bit 2: Bit 1: Bit 0: IOC3 IOC2 ...
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Channel 1 (TIOR1 Register): Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR1B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 ...
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Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR1A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 ...
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Channel 2 (TIOR2 Register): Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR2B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 ...
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Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR2A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 ...
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Timer Interrupt Enable Register (TIER) The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel. The MTU has three TIER registers, one each for channel. TIER is initialized to H' power- ...
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Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when the TGFD bit of the channel 0 of the TSR register is set to 0. This bit is reserved for channels 1 and 2. It always reads ...
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Timer Status Register (TSR) The timer status register (TSR 8-bit register that indicates the status of each channel. The MTU has three TSR registers, one each for channel. TSR is initialized to H' power-on reset. ...
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Bit 3—Output Compare Flag D (TGFD): This status flag indicates the occurrence of a channel 0 TGRD register compare-match. This bit is reserved in channels 1 and 2: it always reads 0 and the write value should always be 0. ...
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Bit 0—Input Capture/Output Compare Flag A (TGFA): This status flag indicates the occurrence of a TGRA register input capture or compare-match. Bit 0: TGFA Description 0 Clear condition: With TGFA = write to TGFA following a read ...
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Timer General Register (TGR) Each timer general register (TGR 16-bit register that can function as either an output compare register or an input capture register. There are a total of eight TGR, four each for channels 0 ...
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Bit n: CSTn Description 0 TCNTn count is halted (initial value) 1 TCNTn counts Note written to a CST bit during operation with the TIOC pin in the output state, the counter ...
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Bit n: SYNCn Description 0 Timer counter (TCNTn) independent operation (initial value) (TCNTn preset/clear unrelated to other channels) 1 Timer counter synchronous operation* TCNTn synchronous preset/ synchronous clear* Note: 1. Minimum of two channel SYNC bits must be set to ...
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Internal data bus Upper 8 bits Bus master Lower 8 bits Figure 8.3 8-Bit Register Access Operation (Bus Master Internal data bus Upper 8 bits Bus master Lower 8 bits Figure 8.4 8-Bit Register Access Operation (Bus Master Internal data ...
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Operation 8.4.1 Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external ...
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Set the TGR selected in step output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in the TGR selected in step 2. 5. Set the CST bit in the ...
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TCNT value H'FFFF H'0000 CST bit TCFV Figure 8.7 Free-Running Counter Operation Periodic Counter Operation Example: Periodic counter operation is obtained for a given channel’s TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for period ...
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Compare-Match Waveform Output Function: The MTU can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. Procedure for selecting the compare-match waveform output operation (figure 8.9): 1. Set the TIOR to select 0 output ...
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TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB Figure 8.10 Example of 0 Output/1 Output Waveform Output Operation (Toggle Output): Figure 8.11 shows the toggle output. In the example, the TCNT operates as a periodic counter cleared by compare-match B, ...
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The procedure for selecting the input capture operation (figure 8.12) is: 1. Set the TIOR to select the input capture function of the TGR, then select the input capture source, and rising edge, falling edge, or both edges as the ...
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Synchronous Operation There are two kinds of synchronous operation, synchronized preset and synchronized clear. The synchronized preset operation allows multiple timer counters (TCNT rewritten simultaneously, while the synchronized clear operation allows multiple TCNT counters to be cleared ...
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Synchronized Operation: Figure 8.15 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter clear upon compare-match with TGR0B. Channels 1 and 2 ...
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Buffer Operation Buffer operation is a function of channel 0. TGRC and TGRD can be used as buffer registers. Table 8.5 shows the register combinations for buffer operation. Table 8.5 Register Combinations Channel 0 The buffer operation differs, depending ...
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Procedure for Setting Buffer Mode (Figure 8.18): 1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output compare register. 2. Use the timer mode register (TMDR) BFA, and BFB bits to ...
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TCNT value TGR0B H'0200 TGR0A H'0000 H'0200 TGR0C Transfer TGR0A H'0200 TIOC0A Figure 8.19 Buffer Operation Example (Output Compare Register) Buffer Operation Examples—when TGR Is an Input Capture Register: Figure 8.20 shows an example of TGRA set as an input ...
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Cascade Connection Mode Cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. This function operates by using the TPSC2–TPSC0 bits of the TCR register to set the ...
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TCNT1 Clock TCNT1 H'03A1 TCNT2 Clock TCNT2 H'FFFF TIOC1A, TIOC2A TGR1A TGR2A Figure 8.22 Cascade Connection Operation Example (Input Capture) 8.4.6 PWM Mode PWM mode outputs the various PWM waveforms from output pins. Output levels of 0 output, 1 output, ...
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Table 8.7 lists the combinations of PWM output pins and registers. Table 8.7 Combinations of PWM Output Pins and Registers Channel Register 0 (AB pair) TGR0A TGR0B 0 (CD pair) TGR0C TGR0D 1 TGR1A TGR1B 2 TGR2A TGR2B Note: PWM ...
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Figure 8.23 Procedure for Selecting the PWM Mode PWM Mode Operation Examples—PWM Mode 1 (Figure 8.24): A TGRA register compare- match is used as a TCNT counter clear source, the TGRA register initial output value and output compare output value ...
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PWM Mode Operation Examples—PWM Mode 2 (Figure 8.25): Channels 0 and 1 are set for synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source, the other TGR register initial output value is 0 and output compare ...
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Duty Cycle: Figure 8.27 shows an example of a 100% duty cycle PWM waveform output in PWM mode. In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of ...
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Interrupts 8.5.1 Interrupt Sources and Priority Ranking The MTU has two interrupt sources: TGR register compare-match/input captures, TCNT counter overflows. Because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the ...
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Table 8.8 MTU Interrupt Sources Channel Interrupt Source 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V 2 TGI2A TGI2B TCI2V TCI2U Note: Indicates the initial status following reset. The ranking of channels can be altered using the interrupt ...
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Operation Timing 8.6.1 Input/Output Timing TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown in figure 8.28. Internal Falling edge clock TCNT input clock N – 1 TCNT Figure 8.28 TCNT Count Timing ...
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TCNT input clock TCNT TGR Compare- match signal TIOC pin Figure 8.29 Output Compare Output Timing (Normal Mode/PWM Mode) Input Capture Signal Timing: Figure 8.30 illustrates input capture timing. Input capture input Input capture signal TCNT TGR Figure 8.30 Input ...
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Counter Clearing Timing Due to Compare-Match/Input Capture: Timing for counter clearing due to compare-match is shown in figure 8.31. Figure 8.32 shows the timing for counter clearing due to input capture. Compare- match signal Counter clear signal TCNT TGR Figure ...
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Buffer Operation Timing: Compare-match buffer operation timing is shown in figure 8.33. Figure 8.34 shows input capture buffer operation timing. TCNT Compare- match signal Compare- match buffer signal TGRA, TGRB TGRC, TGRD Figure 8.33 Buffer Operation Timing (Compare-Match) Input capture ...
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Interrupt Signal Timing Setting TGF Flag Timing during Compare-Match: Figure 8.35 shows timing for the TGF flag of the timer status register (TSR) due to compare-match, as well as TGI interrupt request signal timing. TCNT input clock TCNT TGR ...
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Setting TGF Flag Timing during Input Capture: Figure 8.36 shows timing for the TGF flag of the timer status register (TSR) due to input capture, as well as TGI interrupt request signal timing. Input capture signal N TCNT TGR TGF ...
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Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed write. Figure 8.38 shows the timing for status flag clearing by the CPU. Address Write signal Status flag Interrupt request ...
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Address Write signal Counter clear signal TCNT Figure 8.39 TCNT Write and Clear Contention Contention between TCNT Write and Increment count-up signal is issued in the T during the TCNT write cycle, TCNT write has priority, and the ...
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Contention between Buffer Register Write and Compare Match compare-match occurs in the T state of the TGR write cycle, data is transferred by the buffer operation from the buffer 2 register to the TGR. On channel 0, the ...
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Contention between TGR Read and Input Capture input capture signal is issued in the T state of the TGR read cycle, the read data is that after input capture transfer (figure 8.42). 1 Address Read signal Input capture ...
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Contention between TGR Write and Input Capture input capture signal is issued in the T state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure 2 8.43). Address Write signal Input ...
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Contention between Buffer Register Write and Input Capture input capture signal is issued in the T state of the buffer write cycle, write to the buffer register does not occur, and 2 buffer operation takes priority (figure 8.44). ...
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Contention Between TGR Write and Compare Match compare-match occurs in the T state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued (figure 8.45). Address Write signal Compare match signal ...
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Address Write signal TCNT2 TGR2A–B Ch2 compare- match signal A/B TCNT1 input clock TCNT1 TGR1A Ch1 compare- match signal A TGR1B Ch1 inputcapture signal B TCNT0 TGR0A–D Ch0 input capture signal A, C Figure 8.46 TCNT2 Write and Overflow Contention ...
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Contention between Overflow and Counter Clearing: If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes precedence. Figure 8.47 shows the operation timing when a TGR compare-match is specified as the ...
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Address Write signal TCNT input clock TCNT TCFV flag Figure 8.48 Contention between TCNT Write and Overflow 8.8 MTU Output Pin Initialization 8.8.1 Operating Modes The MTU has the following three operating modes. Waveform output is possible in all ...
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Reset Start Operation The MTU output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin ...
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Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc. When making a transition to a mode (Normal, PWM1, PWM2) in which the pin output level is selected by the timer I/O control register (TIOR) ...
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Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.49 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after ...
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Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.50 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode ...
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Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 8.51 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode ...
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Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 8.52 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal ...
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Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.53 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in ...
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Operation when Rrror Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.54 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in ...
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Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 8.55 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal ...
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Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.56 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in ...
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Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.57 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in ...
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Section 9 8-Bit Timer 1 (TIM1) 9.1 Overview 8-bit timer 1 (TIM1 single-channel interval timer that generates an interval timer interrupt each time the counter overflows. 9.1.1 Features 8-bit interval timer Generates interval timer interrupts An interval timer ...
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Block Diagram Figure 9.1 shows a block diagram of 8-bit timer 1 (TIM1). ITI Interrupt (interrupt control request signal) T1CSR: Timer 1 control/status register T1CNT: Timer 1 counter Figure 9.1 Block Diagram of 8-Bit Timer 1 164 Overflow Clock ...
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Register Configuration 8-bit timer 1 (TIM1) has two registers, as shown in table 9.1. These registers perform clock selection and other functions. Table 9.1 8-Bit Timer 1 Registers Name Abbreviation Timer 1 control/ T1CSR status register Timer 1 counter ...
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Timer 1 Control/Status Register (T1CSR) The timer 1 control/status register (T1CSR 8-bit readable/writable* register that selects the clock to be input to the timer 1 counter (T1CNT) and the timer mode. Bits 7, 5, and 2 through ...
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Bit 2: Bit 1: Bit 0: CKS2 CKS1 CKS0 Note: The overflow period is the time from when T1CNT starts counting up from H'00 until overflow ...
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Reading T1CNT and T1CSR: These registers are read in the same way as other registers. The read addresses are H'FFFF8610 for T1CSR and H'FFFF8611 for T1CNT. A byte transfer instruction must be used to read these registers. 9.3 Operation 9.3.1 ...
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Timing of Overflow Flag (OVF) Setting When the timer 1 counter (T1CNT) overflows, the OVF bit is set the timer 1 serial control register (T1CSR) and, at the same time, an interval timer interrupt (ITI) is ...
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Usage Notes 9.4.1 Contention between Timer 1 Counter (TCNT) Write and Increment If a timer 1 counter clock pulse is generated during the T3 state of a timer 1 counter (TCNT) write cycle, the data write to T1CNT takes ...
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Section 10 8-Bit Timer 2 (TIM2) 10.1 Overview 8-bit timer 2 (TIM2 single-channel interval timer that generates compare match interrupts. 10.1.1 Features 8-bit interval timer Generates compare match interrupts A compare match interrupt is generated by a counter ...
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Block Diagram Figure 10.1 shows a block diagram of 8-bit timer 2 (TIM2). CMI Interrupt (interrupt control request signal) Comparator T2COR T2CSR: Timer 2 control/status register T2CNT: Timer 2 counter T2COR: Timer 2 constant register Figure 10.1 Block Diagram ...
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Table 10.1 8-Bit Timer 2 Registers Name Timer 2 control/status register Timer 2 counter Timer 2 constant register 10.2 Register Descriptions 10.2.1 Timer 2 Control/Status Register (T2CSR) The timer 2 control/status register (T2CSR 16-bit readable/writable* register that selects ...
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Bit 5—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests initiated by the CMF flag when set T2CSR. Bit 5: CMIE Description 0 Interrupt request by CMF flag disabled (initial value) 1 Interrupt request by CMF ...
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Bit: 15 — Initial value: 0 R/W: R Bit: 7 Initial value: 0 R/W: R/W 10.2.3 Timer 2 Constant Register (T2COR) The timer 2 constant register (T2COR 16-bit readable/writable register that is used to set the T2CNT compare ...
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Operation 10.3.1 Cyclic Count Operation When a clock is selected with bits CKS2–CKS0 in the T2CSR register, the T2CNT counter starts incrementing on the selected clock. When the T2CNT counter value matches the value in the timer 2 constant ...
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Interrupts 10.4.1 Interrupt Source When interrupt request flag CMF is set to 1, and interrupt enable bit CMIE is also 1, the corresponding interrupt request is output. 10.4.2 Timing of Compare Match Flag Setting The CMF bit in the ...
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Timing of Compare Match Flag Clearing The CMF bit in the T2CSR register is cleared by reading the bit when it is set to 1, then writing 0 in it. Figure 10.5 shows the timing of CMF bit clearing ...
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Section 11 Compare Match Timer (CMT) 11.1 Overview The SH7011 has an on-chip compare match timer (CMT) configured of 16-bit timers for two channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 11.1.1 Features The CMT ...
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Block Diagram Figure 11.1 shows a block diagram of the CMT. CM10 Control circuit CMSTR: Compare match timer start register CMCSR: Compare match timer control/status register CMCOR: Compare match timer constant register CMCNT: Compare match timer counter CMI: Compare ...
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Register Configuration Table 11.1 summarizes the CMT register configuration. Table 11.1 Register Configuration Channel Name Shared Compare match timer start register 0 Compare match timer control/status register 0 Compare match timer counter 0 Compare match timer constant register 0 ...
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Register Descriptions 11.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT initialized to ...
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Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation initialized ...
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Bits 1, 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock ( ). When the STR bit of the CMSTR is set ...
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Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by power-on resets. Bit: 15 Initial value: ...
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CMCNT Count Timing One of four clocks ( /8, /32, /128, /512) obtained by dividing the system clock (CK) can be selected by the CKS1, CKS0 bits of the CMCSR. Figure 11.3 shows the timing. CK Internal clock CMCNT ...
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CK CMCNT input clock CMCNT CMCOR Compare match signal CMF CMI 11.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared either by writing after reading a 1. Figure 11.5 shows ...
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Notes on Use Take care that the contentions described in sections 11.5.1–11.5.3 do not arise during CMT operation. 11.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T CMCNT counter clear ...
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Contention between CMCNT Word Write and Incrementation If an increment occurs during the T write has priority increment occurs. Figure 11.7 shows the timing. CK Address Internal write signal Compare match signal CMCNT Figure 11.7 CMCNT Word ...
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Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T priority increment of the write data results on the writing side. The byte data on the side not performing the writing is also ...