HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 52

MPU 5V 0K 100-QFP

HD6417011VX20V

Manufacturer Part Number
HD6417011VX20V
Description
MPU 5V 0K 100-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7010r
Datasheet

Specifications of HD6417011VX20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
POR, PWM
Number Of I /o
11
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417011VX20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.1
The clock pulse generator (CPG) supplies clock pulses within the SH7011 and to external devices.
The SH7011’s CPG operates the SH7011 at a frequency equal to the oscillation frequency of the
crystal resonator. The CPG is composed of an oscillator and a duty adjustment circuit (figure 4.1).
There are two ways of generating a clock with the CPG: by connecting a crystal resonator, or by
inputting an external clock.
4.2
Either a crystal resonator or an external clock can be selected as the clock pulse source.
4.2.1
Circuit Configuration: Figure 4.2 shows the method of connecting a crystal resonator. Use the
damping resistance (Rd) shown in table 4.1. An AT-cut parallel-resonance type crystal resonator
with the same frequency as the system clock (CK) should be used. Load capacitors (C
be connected as shown in the figure.
The clock pulses generated by the crystal resonator and internal oscillator are sent to the duty
adjustment circuit. After the duty has been adjusted, the pulses are supplied within the SH7011
chip and to external devices.
XTAL
EXTAL
CK (system
clock)
Overview
Clock Source
Crystal Resonator Connection
Section 4 Clock Pulse Generator (CPG)
Oscillator
Figure 4.1 CPG Block Diagram
Duty adjustment
circuit
CPG
L1
Internal
clock ( )
, C
L2
) must
41

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