HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 79

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.4
6.4.1
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. The interrupt controller detects the interrupt request sent from the interrupt controller when it
5. The status register (SR) and program counter (PC) are saved onto the stack.
6. The priority level of the accepted interrupt is written to bits I3–I0 in SR.
7. The CPU reads the start address of the exception service routine from the exception vector
Note: An interrupt request for which edge detection has been set is held pending until it is
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following the priority levels set in interrupt priority level setting registers A–H (IPRA–IPRH).
Lower-priority interrupts are ignored*. If a number of interrupts with the same priority level
occur, or if multiple interrupts occur within a single module, the interrupt with the highest
default priority or the highest priority within its IPR setting range (as indicated in table 6.3) is
selected.
interrupt mask bits (I3–I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3–I0, the request is ignored. If the request priority level is
higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU.
decodes the next instruction to be executed. Instead of executing the decoded instruction, the
CPU starts interrupt exception processing (figure 6.4).
table for the accepted interrupt, jumps to that address, and starts executing the program there.
This jump is not a delay branch.
accepted. However, an IRQ interrupt can be cleared by an IRQ status register (ISR)
access. For details see section 6.2.3, IRQ Interrupts.
Pending edge-detected interrupts are cleared by a power-on reset.
Interrupt Operation
Interrupt Sequence