HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 204

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.2.2
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset.
12.2.3
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB
(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data
from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,
however, the SCI does not load the TDR contents into the TSR.
The CPU cannot read or write the TSR directly.
12.2.4
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When
the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the
TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset.
194
Initial value:
Receive Data Register (RDR)
Transmit Shift Register (TSR)
Transmit Data Register (TDR)
R/W:
R/W:
Bit:
Bit:
—
7
0
R
7
—
6
0
R
6
—
5
0
R
5
—
4
0
R
4
—
3
0
R
3
—
2
0
R
2
—
1
0
R
1
—
0
0
R
0