HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 227

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
Figure 12.5 shows an example of SCI transmit operation.
Receiving Serial Data: Figures 12.6 show a sample flowchart for receiving serial data. The
procedure is as follows (the steps correspond to the numbers in the flowchart).
1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,
2. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF
3. Continue receiving serial data: Read the RDR and RDRF bit and clear RDRF to 0 before the
Figure 12.5 SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Marking: output of 1 bits continues until the start bit of the next transmit data.
data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then
continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR
is set to 1, a transmit-end interrupt (TEI) is requested.
and FER bits of the SSR to identify the error. After executing the necessary error handling,
clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain
set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
stop bit of the current frame is received.
TDRE
TEND
Serial
data
interrupt
request
1
TxI
Start
bit
0
handler writes
data in TDR
TxI interrupt
and clears
TDRE to 0
D0 D1
1 frame
Data
D7
Parity
TxI interrupt
bit
0/1
request
One Stop Bit)
Stop
bit
1
Start
bit
0
D0
D1
Data
D7 0/1
TEI interrupt request
Parity
bit
Stop
bit
1
(marking
state)
Idle
1
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