HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 25

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Word or longword immediate data is not located in the instruction code, but instead is stored in a
memory table. An immediate data transfer instruction (MOV) accesses the memory table using the
PC relative addressing mode with displacement.
2.3
2.3.1
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using
the pipeline system. Instructions are executed in 50 ns at 20 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data (table 2.2).
Table 2.2
SH7011 CPU
MOV.W
ADD
.DATA.W
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the
instruction that follows the branch instruction and then branching reduces pipeline disruption
during branching (table 2.3). There are two types of conditional branch instructions: delayed
branch instructions and ordinary branch instructions.
Instruction Features
RISC-Type Instruction Set
R1,R0
H'1234
@(disp,PC),R1
.........
Sign Extension of Word Data
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Example of Conventional CPU
ADD.W
#H'1234,R0
13