HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 19

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

1.3.2
Table 1.1 lists the pin functions.
Table 1.1
Classification
Power supply
Clock
System control
Interrupts
Address bus
Data bus
Bus control
6
Pin Functions
Pin Functions
Symbol
V
V
EXTAL
XTAL
CK
RES
NMI
IRQ0–IRQ7 I
A1–A21
D0–D15
CS0 to CS3 O
RD
WRH
WRL
WAIT
CC
SS
I/O
I
I
I
I
O
I
I
O
I/O
O
O
O
I
Name
Supply
Ground
External clock
Crystal
System clock
Power-on reset
Non-maskable
interrupt
Interrupt
requests 0–7
Address bus
Data bus
Chip selects 0–3 Chip select signals for external
Read
Upper write
Lower write
Wait
Function
Connects to power supply.
Connect all V
supply. No operation will occur if there
are any open pins.
Connects to ground.
Connect all V
ground. No operation will occur if there
are any open pins.
Connect a crystal oscillator. Also, an
external clock can be input to the
EXTAL pin.
Connect a crystal oscillator.
Supplies the system clock to
peripheral devices.
Power-on reset when low
Non-maskable interrupt request pin.
Enables selection of whether to accept
on the rising or falling edge.
Maskable interrupt request pins.
Allows selection of level input and
edge input.
Outputs addresses.
16-bit bidirectional data bus.
memory or devices.
Indicates reading from an external
device.
Indicates writing the upper 8 bits (15–
8) of external data.
Indicates writing the lower 8 bits
(7–0) of external data.
Input causes insertion of wait cycles
into the bus cycle during external
space access.
CC
SS
pins to the system
pins to the system