HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 158

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.4.2
Internal interrupts issued from the on-chip peripheral modules have the following features:
1. For each on-chip peripheral module there are flags that indicate the interrupt request status,
2. The control level for each interrupt can be set by ICR.
3. The DTC can be activated by an interrupt request from an on-chip peripheral module.
4. An interrupt request that activates the DTC is not affected by the interrupt control mode or the
5.5
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and
UI bits in CCR are given priority and processed before interrupt requests from modules that are set
to control level 0 (no priority).
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REJ09B0300-0300
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
status of the CPU interrupt mask bits.
Internal Interrupts
Interrupt Exception Handling Vector Table