HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 499

IC H8S MCU FLASH 256K 100-QFP

HD64F2145BTE20

Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of HD64F2145BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Table 16.6 I
Legend
S
SLA
R/W
A
DATA
P
SDA
SCL
S
Start condition. The master device drives SDA from high to low while SCL is high
Slave address. The master device selects the slave device.
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
Stop condition. The master device drives SDA from low to high while SCL is high
2
C Bus Data Format Symbols
FS=1 and FSX=1
SLA
1–7
S
1
Figure 16.5 I
R/W
8
DATA
8
1
A
9
Figure 16.6 I
2
C Bus Data Format (Serial Format)
DATA
n
1–7
DATA
m
2
C Bus Timing
8
Section 16 I
Rev. 3.00 Mar 21, 2006 page 443 of 788
9
A
P
1
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = from 1)
2
C Bus Interface (IIC) (Optional)
1–7
DATA
8
REJ09B0300-0300
A/A
9
P

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