HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 392
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 13 Timer Connection
13.4.5
IVI Signal Fall Modification and IHI Synchronization
By using the timer connection facility and TMR_1, the fall of the IVI signal can be shifted
backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be
synchronized with the rise of the IHI signal.
To perform 8-bit timer divided waveform period measurement, TCNT in TMR_1 is set to count
external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal
(inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is
written in TCORB.
Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the
IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When
fall modification is selected, a reset is performed on a TMR_1 TCORB compare-match in
TMR_1.
The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal,
regardless of whether or not fall modification is selected.
Examples of TCR, TCSR, and TCORB settings in TMR_1 are shown in table 13.8, and the fall
modification/IHI synchronization timing chart is shown in figure 13.7.
Rev. 3.00 Mar 21, 2006 page 336 of 788
REJ09B0300-0300
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