DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 151
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 151 of 1048
- Download datasheet (6Mb)
Table 2.10 Block Data Transfer Instructions
Instruction
EEPMOV.B
EEPMOV.W
2.6.2
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation Field
• Register Field
• Effective Address Extension
• Condition Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
Size
⎯
⎯
Function
if R4L ≠ 0 then
else next;
if R4 ≠ 0 then
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Repeat @ER5+ → @ER6+
Until R4L = 0
Repeat @ER5+ → @ER6+
Until R4 = 0
R4L–1 → R4L
R4–1 → R4
Rev. 6.00 Mar. 18, 2010 Page 89 of 982
REJ09B0054-0600
Section 2 CPU
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