DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 198
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Interrupt Controller
The detection of IRQn interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt
request flag is set to 1 when the setting condition is satisfied, regardless of IER settings.
Accordingly, refer to only necessary flags.
5.4.2
Internal interrupts that are requested from the on-chip peripheral modules have the following
features.
• For each on-chip peripheral module, there are flags that indicate the interrupt request status,
• The interrupt priority level can be set with IPR.
• TPU and SCI interrupt requests can activate the DMAC* or DTC. When the DMAC* or DTC
Note: * Supported only by the H8S/2239 Group.
5.4.3
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. Modules set at the same priority will
conform to their default priorities. Priorities within a module are fixed.
Rev. 6.00 Mar. 18, 2010 Page 136 of 982
REJ09B0054-0600
and enable bits that select enabling or disabling of these interrupts, and they are masked
independently. If the enable bit is set to 1 for a particular interrupt source, an interrupt request
is issued to the interrupt controller.
is activated by the interrupt request, the interrupt control mode and CPU interrupt mask bits are
disregarded.
IRQn
input pin
IRQnF
Internal Interrupts
Interrupt Exception Handling Vector Table
Note: n = 7 to 0
Figure 5.3 Set Timing for IRQnF
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