DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 596
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
(c) Setting the IEBus Slave Address Setting Registers 1 and 2 (IESA1 and IESA2)
(d) Setting the IEBus Master Control Register (IEMCR)
(e) Setting the IEBus Receive Interrupt Enable Register (IEIER)
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2) DTC Initialization
1. Set the start address of the RAM which stores the register information necessary for the DTC
2. Set the following data from the start address of the RAM.
3. Set bit DTCEG6 in the DTC enabler register G (DTCERG), and enable the RxRDY interrupt
Because the above settings are performed before frame reception, the length of data to be received
cannot be determined. Accordingly, the maximum number of transfer bytes in one frame is
specified as the DTC transfer count.
If the DTC is specified after reception starts, the above settings are performed in the receive start
detection (RxS) interrupt handling routine. In this case, the transfer count must be the same value
as the contents of the IEBus receive message length register (IERBFL).
Rev. 6.00 Mar. 18, 2010 Page 534 of 982
REJ09B0054-0600
Specify the communications destination slave unit address.
Select broadcast/normal communications, specify the number of retransfer counts at arbitration
loss, and specify the control bits.
Enable the RxRDY (IERxI), RxS, RxF, and RxE (IERSI) interrupts.
transfer in the vector address (H'000004D2) to be accessed when a DTC transfer request is
generated.
⎯ Transfer source address (SAR): Address (H'FFF80D) of the IEBus receive buffer register
⎯ Transfer destination address (DAR): Start address of the RAM which stores data to be
⎯ Transfer count (CRA): Maximum number of transfer bytes in one frame in the transfer
(IERxI).
(IERBR).
received from the data field.
mode.
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