DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 317
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
Figure 8.17 shows an example of the setting procedure for block transfer mode.
and transfer destination
Set number of transfers
Figure 8.17 Example of Block Transfer Mode Setting Procedure
Block transfer mode
Set transfer source
Read DMABCRL
Set DMABCRH
Set DMABCRL
Block transfer
mode setting
Set DMACR
addresses
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Set each bit in DMABCRH.
Set the transfer source address in MARA, and
the transfer destination address in MARB.
Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
Set each bit in DMACRA and DMACRB.
Read DTE = 0 and DTME = 0 in DMABCRL.
Set each bit in DMABCRL.
Set the FAE bit to 1 to select full address
mode.
Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Set the transfer data size with the DTSZ bit.
Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
Set the BLKE bit to 1 to select block transfer
mode.
Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
Select the activation source with bits DTF3 to
DTF0.
Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Rev. 6.00 Mar. 18, 2010 Page 255 of 982
Section 8 DMA Controller (DMAC)
REJ09B0054-0600
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