DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 696
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
• Wait function in slave mode
• Interrupt sources
• Selection of 16 internal clocks (in master mode)
• Direct bus drive
Figure 16.1 shows a block diagram of the I
pin connections to external circuits. Channel I/O pins are NMOS open drains, and it is possible to
apply voltages in excess of the power supply (Vcc) voltage for this LSI. Set the upper limit of
voltage applied to the power supply (Vcc) power supply range +0.3 V. Channel 1 I/O pins are
driven solely by NMOS, so in terms of appearance they carry out the same operations as an
NMOS open drain. However, the voltage which can be applied to the I/O pins depends on the
voltage of the power supply (Vcc) of this LSI.
Rev. 6.00 Mar. 18, 2010 Page 634 of 982
REJ09B0054-0600
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
⎯ Data transfer end (including transmission mode transition with I
⎯ Address match: when any slave address matches or the general call address is received in
⎯ Start condition detection (in master mode)
⎯ Stop condition detection (in slave mode)
⎯ Two pins, P35/SCL0 and P34/SDA0, function as NMOS open-drain outputs when the bus
⎯ Two pins, P33/SCL1 and P32/SDA1, function as NMOS-only outputs when the bus drive
reception after loss of master arbitration)
slave receive mode
drive function is selected.
function is selected.
2
C Bus Interface (IIC) (Option)
2
C bus interface. Figure 16.2 shows an example of I/O
2
C bus format and address
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