DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 599
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(c) Setting the IEBus Transmit Message Length Register (IETBFL)
(d) Setting the IEBus Transmit/Runaway Interrupt Enable Register (IEIET)
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2) DTC Initialization
1. Set the start address of the RAM which stores the register information necessary for the DTC
2. Set the following data from the start address of the RAM.
3. Set bit DTCEG5 in the DTC enabler register G (DTCERG), and enable the TxRDY interrupt
(3) Slave Transmission Flow
Figure 14.12 shows the slave transmission flow. Numbers in the following description correspond
to the numbers in Figure 14.12.
1. After the IEB and DTC have been initialized, a slave communications request command is
2. The CMX flag is cleared when the slave reception is completed, the slave communications
3. If data up to the control field has been received correctly and if the contents of the control bits
4. The slave then transmits the message length field, and the IEB loads the transmit data in the
Specify the message length bits.
Enable the TxRDY (IETxI), TxS, and TxE (IETSI) interrupts.
transfer in the vector address (H'000004D4) to be accessed a DTC transfer request is
generated.
⎯ Transfer source address (SAR): Start address of the RAM which stores data to be
⎯ Transfer destination address (DAR): Address (H'FFF808) of the IEBus transmit buffer
⎯ Transfer count (CRA): The same value as IETBFL
(IETxI).
Because the TxRDY flag is retained after reset, the DTC transfer is executed when the IETxI is
enabled and the first data field data is written to IETBR. The DTC negates the TxRDY flag
and the DTC transfer of the first byte is completed.
issued from IECMR. During slave reception, the command execution status flag (CMX) in
IEFLG is set and the slave communications request will not be issued.
command is executed, and the SRQ flag is set.
is H'3 or H'7, the transmit start detection flag (TxS) in IETSR register is set to 1. In this case,
the TxS flag is cleared in the TxS interrupt handling routine.
data field from IETBR when the ACK is received. Then the TxRDY flag is set to 1. A DTC
transmitted from the data field.
register (IETBR)
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 537 of 982
REJ09B0054-0600
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