DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 186
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 4 Exception Handling
Table 4.4
Interrupt Control Mode
0
2
Legend:
1:
0:
—:
4.5
Interrupts are controlled by the interrupt controller. The interrupt control has two interrupt control
modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. For details, refer to section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Rev. 6.00 Mar. 18, 2010 Page 124 of 982
REJ09B0054-0600
register (EXR) are saved to the stack.
from the vector table to the PC, and program execution begins from that address.
register (EXR) are saved to the stack.
from the vector table to the PC, and program execution starts from that address.
Set to 1
Cleared to 0
Retains value prior to execution
Trap Instruction
Interrupts
Status of CCR and EXR after Trace Exception Handling
CCR
I
Trace exception handling cannot be used.
1
UI
—
—
EXR
I2 to I0
0
T
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